Tags	No category tags.
Version	0.3.0
License	Apache License 2.0
Build type	AMENT_CMAKE
Use	RECOMMENDED

Description	ROS 2 package examples demonstrating the use of hardware acceleration.
Checkout URI	https://github.com/ros-acceleration/acceleration_examples.git
VCS Type	git
VCS Version	main
Last Updated	2024-12-13
Dev Status	UNKNOWN
CI status	No Continuous Integration
Released	UNRELEASED
Tags	fpga gpu hardware-acceleration ros2
Contributing	Help Wanted (0) Good First Issues (0) Pull Requests to Review (0)

A trivial double vector-add ROS 2 publisher that adds two inputs to a vector in a loop and attempts to publish them on the go at 10 Hz. Vector add operations are offloaded into to the FPGA. This example builds on top of "doublevadd_publisher" which is only able to publish at 2 Hz on the quad-core Cortex-A53 Application Processing Units (APUs) of the Zynq Ultrascale+ (ZU+) SoC. The acceleration operation into the FPGA (or to the Programmable Logic (PL)) allows the publisher to improve its publishing rate from 2 Hz, up to 6 Hz. For that, the HLS INTERFACE pragma is used. The HLS INTERFACE specifies how RTL ports are created from the function definition during interface synthesis. Sharing ports helps save FPGA resources by eliminating AXI interfaces, but it can limit the performance of the kernel because all the memory transfers have to go through a single port. The m_axi port has independent READ and WRITE channels, so with a single m_axi port, we can do reads and writes simultaneously but since the kernel (vadd) has two vectors from where its reading (simultaneously), we can optimize the dataflows by simply asking for an extra AXI interface. After using the PL, accelerated_doublevadd_publisher is able to publish at 6 Hz in the ZU+, still far from its targeted rate (10 Hz). See "doublevadd_publisher" for a version running purely on the APUs (2 Hz). See "faster_doublevadd_publisher" for yet another version of this publisher which further leverages parallelism to meet the targeted rate (10 Hz).

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• Víctor Mayoral Vilches

• Víctor Mayoral Vilches